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Thread: USB Bitbanger with AVR, Good for NOR flash programming etc.
  

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  1. #21  
    rikimaer is offline Registered User
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    Will be compatible at90usbkey?


    Have about 50 I/O.

    Thanks
    Best Regards.
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  2. #22  
    heretic is offline Registered User
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    hi everybody ! i need a help to find tihis pinout for test points in my 40GB

    it's a SEM-001

    http://psx-scene.com/forums/attachme...1&d=1295868706

    [IMG]
    http://psx-scene.com/forums/attachme...1&d=1295868706
    [/IMG]
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  3. #23  
    joohan is offline Registered User
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    Quote Originally Posted by jessolox View Post
    It's strange... cause the NOR isn't encrypted! Only the files that are inside are. So you maybe have done something wrong. BTW if you can post your code it would be great!
    I had swapped some data lines, and the endiannes was wrong but now it works.

    And if someone finds the source useful then here you are.
    Connect the lines according to the posted schematic, and ce, oe etc can be easily configured in the source, as long as it is on PORTE

    It depends on LUFA ( not included )

    the protocol so far:
    read block: r+[blocknumber]
    read all blocks r+[decimal 229]
    Attached Files
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  4. #24  
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    ...
    Last edited by ieder-zijn-meis; 07-06-2011 at 10:14 PM.
    Appldr NPDRM 1.00-3.31 (rev 0x01):00 040AB475 09BED04B D96521AD 1B365B86 BF620A98 / 3.40-3.42 (rev 0x04):00 B61A91DF 4AB6A9F1 42C326BA 9592B526 5DA88856 / 3.50-3.55 (rev 0x07):00 9EF86907 782A318D 4CC3617E BACE2480 E73A46F6
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  5. #25  
    cmal1492 is offline aka cory1492
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    Quote Originally Posted by ieder-zijn-meis View Post
    But if your board is SEM-001, then it is model CECHG, type 0x05 with 256MB NAND interleaved on 2 chips (Samsung K9F1G08U0A-PIB0), not NOR in single noninterleaved 16MB chip (Spansion S29GL128N90TFIR2 or Samsung K8Q2815UQB-P14B). See:
    ieder-zijn-meis, the dual NAND PS3 has a NOR emulation chip and the PS3 sees dual NAND as 256M NOR (it was interleaved to make up for the speed differences between NOR and NAND), as far as I can tell the test points still correspond to NOR access - unless you are lifting the NAND or wiring directly to the NAND it may be possible to still access these via those point without dealing with the NAND ecc/edc stuff.
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  6. #26  
    Gee99x's Avatar
    Gee99x is offline Registered User
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    Hey joohan thanks for the board layout. What ext. clock speed are you using and what are the capacitor values on this board?
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  7. #27  
    heretic is offline Registered User
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    Quote Originally Posted by ieder-zijn-meis View Post
    Good job
    jessolox / jestero for the NOR points on CECHL04 (Spansion S29GL128N90TFIR2)
    and joohan for debugging/posting sources



    Attachement error...

    [lang=it]here my pinout help plz !! =) it's totaly different

    http://www.nextrl.it/forum/index.php...attach_id=1279[/lang]
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  8. #28  
    joohan is offline Registered User
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    Quote Originally Posted by Gee99x View Post
    Hey joohan thanks for the board layout. What ext. clock speed are you using and what are the capacitor values on this board?
    Clock speed should be max 8Mhz for 3.3V ( according to AVR datasheet ), And only 8 or 16Mhz is "compatible" with the USB device. So 8Mhz is the only choice.
    BUT I used 16Mhz, only because I was out of 8Mhz and it does work but I would not recommend it.

    About the caps, around 12-20p for the XTAL and the rest anything 100n -> 1u should be ok.

    And the resistors are only there to limit current so they are not critical.
    You might connect HWB to ground (preferably through a resistor) that way it will enter bootloader on external reset, but NOT on bod or por reset. (This is an undocumented feature) Quite nice since then you will only need one switch for programming.
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  9. #29 Thumbs up  
    Gee99x's Avatar
    Gee99x is offline Registered User
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    Thanks for that. Kudos for your work.
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  10. #30  
    IceKiller is offline Registered User
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    Anyone here have a NOR dump could pm me thx.
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